1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a decoupling capacitor (on chip capacitor).
2. Description of Related Art
With increasing number of devices and higher speed of LSI (Large Scale Integration), the problem of power supply noise is becoming serious. As a countermeasure against this power supply noise, the method of connecting a power source line and a ground line by a decoupling capacitor is known. The decoupling capacitor is required to follow various noises with different frequencies.
Meanwhile, the decoupling capacitor is playing an important role as an ESD (Electrostatic Discharge) protection device. In recent years, the countermeasure against ESD for the decoupling capacitor itself is posing a serious problem due to a thinner gate insulating film. Therefore, a decoupling capacitor which satisfies both aspects of the countermeasure for noise and ESD is needed.
The techniques of reducing the power supply noise using conventional decoupling capacitors are explained here. Japanese Unexamined Patent Application Publication No. 2006-101254 (Kajita) discloses the technique to form a resonant circuit and a low pass filter using a decoupling capacitor so as to attempt reducing the noise of various frequencies. In the technique disclosed by Kajita, a power source line is resonated compulsorily by the resonant circuit formed of a decoupling capacitor and coil to concentrate noise near resonance frequency. Then, the noise concentrated near the resonance frequency is attenuated by the low pass filter formed of resistance and a capacitor.
Generally, a decoupling capacitor is disposed to a “vacant area” where no other devices are not disposed, after disposing a circuit block. A change in the circuit size and capacity to mount may cause insufficient noise reduction effect by the decoupling capacitor. Therefore, Japanese Unexamined Patent Application Publication No. 2006-040962 (Ogawa) discloses the method of disposing a decoupling capacitor in the chip. Specifically, the method is to secure a decoupling capacitor necessary for each unit area and efficiently carry out the disposing work. Moreover, Japanese Unexamined Patent Application Publication No. 2001-284526 (Kasahara) discloses the technique to improve the frequency characteristic of MIM capacitance. Generally, the frequency characteristics are known to be influenced by the shape of a capacitor.
Next, the role of a decoupling capacitor as an ESD protection device is described. FIG. 6 shows the configuration of a semiconductor integrated circuit device using a conventional decoupling capacitor. As shown in FIG. 6, a plurality of decoupling capacitors C, which are MOS capacitances, are provided between a power source line connected to a power supply terminal Vcc and a ground line connected to a ground terminal GND. Note that in FIG. 6, the plurality of decoupling capacitors are expressed as one decoupling capacitor.
Moreover, an ESD protection device (power supply protection device) is provided between the power source line and the ground line and an ESD protection device (input protection device) is provided between an input terminal IN and the ground line. Here, a case is explained in which electrostatic surge is applied between the power supply terminal Vcc and the ground terminal GND as an example. Although electrostatic surge is discharged through a power supply protection device, it is also charged to a decoupling capacitor immediately after the electrostatic surge is applied so as to prevent an excessive current from flowing into the power supply protection device.
Moreover, a case is explained in which electrostatic surge is applied between the power supply terminal Vcc and the input terminal as another example. The discharge path in this case is; power supply terminal Vcc <=> power supply protection device/decoupling capacitor <=> ground line <=> input protection device <=> input terminal IN. Although whether the electrostatic surge passes through the decoupling capacitor C, the power supply protection device or both of them at the same time depends on the layout, the decoupling capacitor C may be a discharge path.
In “DENGEN KURANPU NI KANSURU KOSATU” by Suzuki et al., November 2005, EOS/ESD/EMC Symposium, 15th RCJ Reliability Symposium Happyo Ronbunsyu, pp.185-190, the relationship between a capacitance value of a decoupling capacitor and ESD robustness is shown when the decoupling capacitor and a protection device (power supply protection device) exist between a power supply terminal and a ground terminal. The technique disclosed by Suzuki et al. indicates that when static electricity is applied between power supply and ground, as the decoupling capacitor does not contribute to electrostatic discharge (ESD) if the capacitance value of the decoupling capacitor is about 1 pF, ESD robustness is determined by the power supply protection device. Moreover, Suzuki et al. indicate that if the capacitance value of the decoupling capacitor is large, about 40 nF, static charge is discharged through the decoupling capacitor. The Suzuki et al. further indicate that if the capacitance value of the decoupling is about 100 pF, which is between 1 pF and 40 nF, the tolerated dose of the power supply protection device decreases under the influence of the operation of the decoupling capacitor.
Moreover, although not shown in FIG. 6, the decoupling capacitor may also be a discharge path at the time of a CDM (Charged device model) test. When considering CDM discharge which is discharged from the power supply terminal Vcc when a semiconductor device of P type substrate is charging, charge by the side of a ground line potential (substrate potential) is discharged through the power supply protection device and a decoupling capacitor.
Japanese Unexamined Patent Application Publication No. 2001-060663 (Horiguchi) discloses the necessity for the ESD protection of MOS capacitance and the configuration of a protection device. Horiguchi indicates that when there is a large potential difference between two electrodes of a MOS capacitance device at the time of a CDM test, protection devices must be provided to appropriate places in order to protect the capacitance device. Moreover, Japanese Unexamined Patent Application Publication No. 2003-86699 (Takamiya) illustrates an example of a ESD countermeasure for a decoupling capacitor itself.
By increasing number of devices and higher speed of LSI, diversification of power supply noise and high frequency noise in each functional block inside a chip are becoming a problem. It is necessary to take frequency characteristics into consideration like Kajita as the countermeasure for these problems. However, as generated noises are different for each circuit, it cannot be supported by one resonant circuit and a filter circuit. Moreover, Ogawa does not support the types of noises (frequency characteristics of a capacitor). Furthermore, although Kasahara takes the frequency characteristics into consideration, Kasahara does not have any suggestion concerning the arrangement of a decoupling capacitor in a chip.
In addition, as indicated by Suzuki et al., since the capacitance value of a decoupling capacitor influences ESD robustness, it must be designed together with ESD robustness of the protection device itself. However, such consideration has not been made for the arrangement of conventional decoupling capacitors.
Furthermore, by a thinner insulating film of a decoupling capacitor (gate insulating film in case of a MOS capacitance), ESD robustness of the decoupling capacitor itself has become a problem. Horiguchi and Takamiya indicate the necessity for protection of a MOS capacitance device. However, both ESD robustness of a decoupling capacitor and noise reduction have not simultaneously been taken into consideration. Especially for a LSI having many power supply and ground terminals, there are various capacitance values of decoupling capacitors between power supply and ground. Therefore, the inventor has now discovered that a configuration which simultaneously satisfies three requirements of noise countermeasure, ESD robustness and ESD protection of a decoupling capacitor itself has not been realized.